June 12, 2021

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Architecture Design for Soft Errors

Architecture Design for Soft Errors
Author : Shubu Mukherjee
Publisher : Morgan Kaufmann Pub
Release Date : 2008
Category : Computers
Total pages :337
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This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem deffinition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. TABLE OF CONTENTS Chapter 1: Introduction Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation Chapter 3: Architectural Vulnerability Analysis Chapter 4: Advanced Architectural Vulnerability Analysis Chapter 5: Error Coding Techniques Chapter 6: Fault Detection via Redundant Execution Chapter 7: Hardware Error Recovery Chapter 8: Software Detection and Recovery * Provides the methodologies necessary to quantify the effect of radiation-induced soft errors as well as state-of-the-art techniques to protect against them

Architecture Design for Soft Errors

Architecture Design for Soft Errors
Author : Shubu Mukherjee
Publisher : Morgan Kaufmann
Release Date : 2011-08-29
Category : Computers
Total pages :360
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Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways this book can be read or used in a course: as a complete course on architecture design for soft errors covering the entire book; a short course on architecture design for soft errors; and as a reference book on classical fault-tolerant machines. This book is recommended for practitioners in semi-conductor industry, researchers and developers in computer architecture, advanced graduate seminar courses on soft errors, and (iv) as a reference book for undergraduate courses in computer architecture. Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors Shows readers how to quantify their soft error reliability Provides state-of-the-art techniques to protect against soft errors

Soft Errors

Soft Errors
Author : Jean-Luc Autran,Daniela Munteanu
Publisher : CRC Press
Release Date : 2015-02-25
Category : Technology & Engineering
Total pages :439
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Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most important primary limits for modern digital electronic reliability. Covering the fundamentals of soft errors as well as engineering considerations and technological aspects, this robust text: Discusses the basics of the natural radiation environment, particle interactions with matter, and soft-error mechanisms Details instrumentation developments in the fields of environment characterization, particle detection, and real-time and accelerated tests Describes the latest computational developments, modeling, and simulation strategies for the soft error-rate estimation in digital circuits Explores trends for future technological nodes and emerging devices Soft Errors: From Particles to Circuits presents the state of the art of this complex subject, providing comprehensive knowledge of the complete chain of the physics of soft errors. The book makes an ideal text for introductory graduate-level courses, offers academic researchers a specialized overview, and serves as a practical guide for semiconductor industry engineers or application engineers.

Achieving High Availability with Commodity Hardware and Software

Achieving High Availability with Commodity Hardware and Software
Author : Nidhi Aggarwal
Publisher : Unknown
Release Date : 2008
Category :
Total pages :118
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Soft-error Mitigation at the Architecture-level Using Berger Codes for Error Detection

Soft-error Mitigation at the Architecture-level Using Berger Codes for Error Detection
Author : Edward John Ossi
Publisher : Unknown
Release Date : 2011
Category : Electronic dissertations
Total pages :54
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FPGAs and Parallel Architectures for Aerospace Applications

FPGAs and Parallel Architectures for Aerospace Applications
Author : Fernanda Kastensmidt,Paolo Rech
Publisher : Springer
Release Date : 2015-12-07
Category : Technology & Engineering
Total pages :325
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This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

Fault Tolerant Network-on-Chip Router Architectures for Multi-Core Architectures

Fault Tolerant Network-on-Chip Router Architectures for Multi-Core Architectures
Author : Pavan Kamal Sudheendra Poluri
Publisher : Unknown
Release Date : 2014
Category :
Total pages :147
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As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the inception of Chip Multiprocessors (CMPs). The widespread use of CMPs has resulted in a paradigm shift from computation-centric architectures to communication-centric architectures. With the continuous increase in the number of cores that can be fabricated on a single chip, communication between the cores has become a crucial factor in its overall performance. Network-on-Chip (NoC) paradigm has evolved into a standard on-chip interconnection network that can efficiently handle the strict communication requirements between the cores on a chip. The components of an NoC include routers, that facilitate routing of data between multiple cores and links that provide raw bandwidth for data traversal. While diminishing feature size has made it possible to integrate billions of transistors on a chip, the advantage of multiple cores has been marred with the waning reliability of transistors. Components of an NoC are not immune to the increasing number of hard faults and soft errors emanating due to extreme miniaturization of transistor sizes. Faults in an NoC result in significant ramifications such as isolation of healthy cores, deadlock, data corruption, packet loss and increased packet latency, all of which have a severe impact on the performance of a chip. This has stimulated the need to design resilient and fault tolerant NoCs. This thesis handles the issue of fault tolerance in NoC routers. Within the NoC router, the focus is specifically on the router pipeline that is responsible for the smooth flow of packets. In this thesis we propose two different fault tolerant architectures that can continue to operate in the presence of faults. In addition to these two architectures, we also propose a new reliability metric for evaluating soft error tolerant techniques targeted towards the control logic of the NoC router pipeline. First, we present Shield, a fault tolerant NoC router architecture that is capable of handling both hard faults and soft errors in its pipeline. Shield uses techniques such as spatial redundancy, exploitation of idle resources and bypassing a faulty resource to achieve hard fault tolerance. The use of these techniques reveals that Shield is six times more reliable than baseline-unprotected router. To handle soft errors, Shield uses selective hardening technique that includes hardening specific gates of the router pipeline to increase its soft error tolerance. To quantify soft error tolerance improvement, we propose a new metric called Soft Error Improvement Factor (SEIF) and use it to show that Shield's soft error tolerance is three times better than that of the baseline-unprotected router. Then, we present Soft Error Tolerant NoC Router (STNR), a low overhead fault tolerating NoC router architecture that can tolerate soft errors in the control logic of its pipeline. STNR achieves soft error tolerance based on the idea of dual execution, comparison and rollback. It exploits idle cycles in the router pipeline to perform redundant computation and comparison necessary for soft error detection. Upon the detection of a soft error, the pipeline is rolled back to the stage that got affected by the soft error. Salient features of STNR include high level of soft error detection, fault containment and minimum impact on latency. Simulations show that STNR has been able to detect all injected single soft errors in the router pipeline. To perform a quantitative comparison between STNR and other existing similar architectures, we propose a new reliability metric called Metric for Soft error Tolerance (MST) in this thesis. MST is unique in the aspect that it encompasses four crucial factors namely, soft error tolerance, area overhead, power overhead and pipeline latency overhead into a single metric. Analysis using MST shows that STNR provides better reliability while incurring low overhead compared to existing architectures.

On-Line Testing Workshop

On-Line Testing Workshop
Author : Anonim
Publisher : IEEE
Release Date : 2002
Category : Computers
Total pages :273
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This text contains information on computer engineering as presented at the 8th IEEE International On-Line Testing Workshop (IOLTW 2002).

Exploring Memory Hierarchy Design with Emerging Memory Technologies

Exploring Memory Hierarchy Design with Emerging Memory Technologies
Author : Guangyu Sun
Publisher : Springer Science & Business Media
Release Date : 2013-09-18
Category : Technology & Engineering
Total pages :122
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This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.

ISLPED'04

ISLPED'04
Author : IEEE Circuits and Systems Society
Publisher : Institute of Electrical & Electronics Engineers(IEEE)
Release Date : 2004
Category : Power electronics
Total pages :400
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"IEEE Catalog Number: 04TH8758"--T.p. verso.

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE
Author : C. Metra
Publisher : Institute of Electrical & Electronics Engineers(IEEE)
Release Date : 2003
Category : Electronic circuit design
Total pages :229
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Dependability in Electronic Systems

Dependability in Electronic Systems
Author : Nobuyasu Kanekawa,Eishi H. Ibe,Takashi Suga,Yutaka Uematsu
Publisher : Springer Science & Business Media
Release Date : 2010-11-08
Category : Technology & Engineering
Total pages :204
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This book covers the practical application of dependable electronic systems in real industry, such as space, train control and automotive control systems, and network servers/routers. The impact from intermittent errors caused by environmental radiation (neutrons and alpha particles) and EMI (Electro-Magnetic Interference) are introduced together with their most advanced countermeasures. Power Integration is included as one of the most important bases of dependability in electronic systems. Fundamental technical background is provided, along with practical design examples. Readers will obtain an overall picture of dependability from failure causes to countermeasures for their relevant systems or products, and therefore, will be able to select the best choice for maximum dependability.

Efficient Techniques for Modeling and Mitigation of Soft Errors in Nanometer-scale Static CMOS Logic Circuits

Efficient Techniques for Modeling and Mitigation of Soft Errors in Nanometer-scale Static CMOS Logic Circuits
Author : Srivathsan Krishnamohan
Publisher : Unknown
Release Date : 2005
Category : Electronic dissertations
Total pages :250
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Electronic Design

Electronic Design
Author : Anonim
Publisher : Unknown
Release Date : 1984
Category : Electronic apparatus and appliances
Total pages :129
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Proceedings

Proceedings
Author : Anonim
Publisher : Unknown
Release Date : 2005
Category : Integrated circuits
Total pages :129
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