June 17, 2021

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High Mobility Materials for CMOS Applications

High Mobility Materials for CMOS Applications
Author : Nadine Collaert
Publisher : Woodhead Publishing
Release Date : 2018-06-29
Category : Technology & Engineering
Total pages :384
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High Mobility Materials for CMOS Applications provides a comprehensive overview of recent developments in the field of (Si)Ge and III-V materials and their integration on Si. The book covers material growth and integration on Si, going all the way from device to circuit design. While the book's focus is on digital applications, a number of chapters also address the use of III-V for RF and analog applications, and in optoelectronics. With CMOS technology moving to the 10nm node and beyond, however, severe concerns with power dissipation and performance are arising, hence the need for this timely work on the advantages and challenges of the technology. Addresses each of the challenges of utilizing high mobility materials for CMOS applications, presenting possible solutions and the latest innovations Covers the latest advances in research on heterogeneous integration, gate stack, device design and scalability Provides a broad overview of the topic, from materials integration to circuits

Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications

Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications
Author : Jacopo Franco,Ben Kaczer,Guido Groeseneken
Publisher : Springer Science & Business Media
Release Date : 2013-10-19
Category : Technology & Engineering
Total pages :187
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Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process - and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

Interface-engineered Ge MOSFETs for Future High Performance CMOS Applications

Interface-engineered Ge MOSFETs for Future High Performance CMOS Applications
Author : Anonim
Publisher : Stanford University
Release Date : 2009
Category :
Total pages :129
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As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, introduction of performance boosters like novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. Detailed characterization of gate dielectric/channel interface and a deeper understanding of mobility degradation mechanisms are needed to address the Ge NMOS performance problem and to improve PMOS performance. In the first part of this dissertation, the electrical characterization results on Ge NMOS and PMOS devices fabricated with GeON gate dielectric are presented. Carrier scattering mechanisms are studied through low temperature mobility measurements. For the first time, the effect of substrate crystallographic orientation on inversion electron and hole mobilities is investigated. Direct formation of a high-k dielectric on Ge has not given good results in the past. A good quality interface layer is required before the deposition of a high-K dielectric. In the second part of this dissertation, ozone-oxidation process is introduced to engineer Ge/insulator interface. Electrical and structural characterizations and stability analysis are carried out and high quality Ge/dielectric interface with low interface trap density is demonstrated. Detailed extraction of interface trap density distribution across the bandgap and close to band edges of Ge, using low temperature conductance and capacitance measurements is presented. Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups worldwide. In spite of the increasing interest in Ge, the major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In the last part of this dissertation, the results on Ge NMOS devices fabricated with the ozone-oxidation and the low temperature source/drain activation processes are discussed. These devices achieve the highest electron mobility to-date, about 1.5 times the universal Si mobility. Detailed interface characterizations, trapping analyses and gated Hall device measurements are performed to identify the mechanisms behind poor Ge NMOS performance in the past.

High-Mobility Group-IV Materials and Devices: Volume 809

High-Mobility Group-IV Materials and Devices: Volume 809
Author : Materials Research Society. Meeting
Publisher : Unknown
Release Date : 2004-08-18
Category : Technology & Engineering
Total pages :304
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The MRS Symposium Proceeding series is an internationally recognised reference suitable for researchers and practitioners. This book, first published in 2004, brings together researchers interested in strained SiGe, strain-relaxed buffers, strained Si on bulk Si and on SOI, SiGe on SOI, Ge substrates, and Ge on insulator.

Reliability of High Mobility Sige Channel Mosfets for Future CMOS Applications

Reliability of High Mobility Sige Channel Mosfets for Future CMOS Applications
Author : Jacopo Franco,Ben Kaczer,Guido Groeseneken
Publisher : Unknown
Release Date : 2013-11-30
Category :
Total pages :208
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Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications

Reliability of High Mobility SiGe Channel MOSFETs for Future CMOS Applications
Author : Jacopo Franco,Ben Kaczer,Guido Groeseneken
Publisher : Springer
Release Date : 2013-10-29
Category : Technology & Engineering
Total pages :187
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Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process - and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

Ultra Clean Processing of Semiconductor Surfaces X

Ultra Clean Processing of Semiconductor Surfaces X
Author : Paul Mertens,Marc Meuris,Marc Heyns
Publisher : Trans Tech Publications Ltd
Release Date : 2012-04-12
Category : Technology & Engineering
Total pages :356
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The International Symposium on Ultra-Clean Processing of Semiconductor Surfaces (UCPSS) is a bi-annual conference which has been organized by IMEC since 1992. Volume is indexed by Thomson Reuters CPCI-S (WoS). The scope of the symposium includes all issues related to contamination, cleaning and surface preparation in mainstream large-scale Integrated Circuit manufacture. At first, silicon was typically the main semiconductor of interest. As other semiconducting materials such as SiGe, SiC, Ge and III-V compounds came under consideration for future devices, the scope was broadened so as to include these materials. Parallelling the fast-moving CMOS industry, the photovoltaic industry has also recognized the need to make improvements in cleaning. Moreover, in order to promote these semiconductor cleaning activities in PV, it was decided to add a special session focused on this topic.

Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates: Volume 1068

Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates: Volume 1068
Author : Materials Research Society. Meeting Symposium C.
Publisher : Materials Research Society
Release Date : 2008-08-29
Category : Technology & Engineering
Total pages :289
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The MRS Symposium Proceeding series is an internationally recognised reference suitable for researchers and practitioners.

High Mobility Strained Si/SiGe Heterostructure MOSFETs

High Mobility Strained Si/SiGe Heterostructure MOSFETs
Author : Christopher William Leitz
Publisher : Unknown
Release Date : 2002
Category : Metal oxide semiconductor field-effect transistors
Total pages :348
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(Cont.) Record mobility strained Si p-MOSFETs have been fabricated on relaxed 40% Ge virtual substrates. Hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with mobility enhancements over twice that of co-processed bulk Si devices. In contrast, hole mobility in strained Si p-MOSFETs displays no strong dependence on strained layer thickness. These results indicate that strain is the primary variable in determining hole mobility in strained Si p-MOSFETs and that symmetric electron and hole mobility enhancements in strained Si MOSFETs can be obtained for virtual substrate compositions beyond 35% Ge. The effect of alloy scattering on carrier mobility in tensile strained SiGe surface channel MOSFETs is measured directly for the first time. Electron mobility is degraded much more severely than hole mobility in these heterostructures, in agreement with theoretical predictions. Dual channel heterostructures, which consist of the combination of buried compressively strained SiilyGey buried channels and tensile strained Si surface channels, grown on relaxed SilxGex virtual substrates, are explored in detail for the first time. Hole mobilities exceeding 700 cm2/V-s have been achieved by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. This layer sequence exhibits nearly symmetric electron and hole mobilities, both enhanced relative to bulk Si ...

Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3

Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3
Author : Z. Karim
Publisher : The Electrochemical Society
Release Date : 2011-04-25
Category :
Total pages :532
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This issue of ECS Transactions will cover the following topics in (a) Graphene Material Properties, Preparation, Synthesis and Growth; (b) Metrology and Characterization of Graphene; (c) Graphene Devices and Integration; (d) Graphene Transport and mobility enhancement; (e) Thermal Behavior of Graphene and Graphene Based Devices; (f) Ge & III-V devices for CMOS mobility enhancement; (g) III.V Heterostructures on Si substrates; (h) Nano-wires devices and modeling; (i) Simulation of devices based on Ge, III-V, nano-wires and Graphene; (j) Nanotechnology applications in information technology, biotechnology and renewable energy (k) Beyond CMOS device structures and properties of semiconductor nano-devices such as nanowires; (l) Nanosystem fabrication and processing; (m) nanostructures in chemical and biological sensing system for healthcare and security; and (n) Characterization of nanosystems; (f) Nanosystem modeling.

McGraw-Hill Yearbook of Science and Technology, 2010

McGraw-Hill Yearbook of Science and Technology, 2010
Author : McGraw-Hill Education
Publisher : McGraw Hill Professional
Release Date : 2010-01-12
Category : Reference
Total pages :496
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Includes coverage of forefront fields such as cell and molecular biology, environmental science, genetics, information technology, nanotechnology, chemistry, and theoretical physics An extensive subject index makes finding information fast and easy Features numerous cross-references to the McGraw-Hill Encyclopedia of Science & Technology and bibliographies of key literature after each article 250+ images, diagrams, and tables enhance the text

Technology for SiGe Heterostructure-based CMOS Devices

Technology for SiGe Heterostructure-based CMOS Devices
Author : Mark Albert Armstrong
Publisher : Unknown
Release Date : 1999
Category : Germanium compounds
Total pages :154
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Bulk silicon is currently the substrate material of choice for the manufacture of high performance digital circuits due to its highly-developed processing technology and the relatively low cost for high-quality substrates. Silicon-based MOSFETs have reached remarkable levels of performance through device scaling. However, with each technology generation, it is becoming harder and harder to improve device performance at the same pace through traditional scaling methods alone. Short-channel effects such as velocity saturation and drain-induced barrier lowering have placed an fundamental limit on the ultimate performance of bulk Si MOSFETS. One way to raise this limit is to increase the carrier mobilities in the channel. This can be done using high-mobility Si and SiGe strained-layers. Unlike III-V-based high-mobility materials, Si/SiGe strained-layers have the advantage of being largely compatible with mainstream Si processing, which is important from a financial feasibility standpoint. This thesis examines several issues related to Si/SiGe strained-layer devices and their integration into mainstream CMOS. The first part of this work strives to predict the performance leverage of high-mobility Si/ SiGe over bulk Si devices and circuits in a realistic manner. Two-dimensional hydrodynamic simulations are used to predict static device characteristics including effects of series resistance, velocity saturation and velocity overshoot. The simulations show enhanced current drive over bulk Si devices at 0.2 [mu]m effective channel length and highlight the importance of velocity overshoot in high-mobility submicron devices. The circuit performance of Si/SiGe devices is determined from transient simulations of CMOS ring oscillators including the effects of parasitic capacitance and drain-to-source voltage at the onset of saturation Vds.sat. The simulations show a 4 to 6-fold reduction in power-delay product as compared to bulk CMOS oscillators operated at 2.5 V with the same design rules. The remainder of the thesis focuses on the fabrication and characterization of strained-Si NMOS devices. The vehicle for this work is a novel short-flow, single-mask MOSFET which can be fabbed in as little as a week. This device is superior to simple Hall mobility structures which suffer from leakage through the substrate, an inability to control the. carrier concentration and the uncertainty associated with the Hall scattering factor. I investigate a novel buried-channel strained-Si NMOS structure incorporating an n-type donor layer beneath the strained-Si channel to encourage occupation of the buried channel and increase the overall mobility. Peak mobility in a structure without a donor layer reproduces the best results in the literature for buried-channel strained-Si NMOS devices. For structures with donor layers, Coulomb scattering from charges in the donor layer eradicates any benefit from increased buried-channel occupation. I also investigate the effect of well implants on the mobility of surface . channel strained-Si NMOS devices. Similar to the universal mobility curve in bulk Si, mobility at low perpendicular electric field degrades with increasing implant dose while high field mobility is unaffected. The mobility is largely unaffected by a neutral implant species at the same dose. This leads to the conclusion that the material quality of the strained-layer is not affected by the implant, and that the mobility degradation is due solely to increased ionized impurity scattering.

III-V Metal-oxide-semiconductor Field-effect-transistors from Planar to 3D

III-V Metal-oxide-semiconductor Field-effect-transistors from Planar to 3D
Author : Fei Xue
Publisher : Unknown
Release Date : 2013
Category :
Total pages :228
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Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices.

A Study of Electrical and Material Characteristics of III-V MOSFETs and TFETs with High-[kappa] Gate Dielectrics

A Study of Electrical and Material Characteristics of III-V MOSFETs and TFETs with High-[kappa] Gate Dielectrics
Author : Han Zhao
Publisher : Unknown
Release Date : 2010
Category :
Total pages :244
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The performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO2 gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al2O3/HfO2 interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO2 gate dielectric with a smaller EOT.

JJAP

JJAP
Author : Anonim
Publisher : Unknown
Release Date : 2009
Category : Physics
Total pages :129
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