June 17, 2021

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Three-Dimensional Integrated Circuit Design

Three-Dimensional Integrated Circuit Design
Author : Vasilis F. Pavlidis,Ioannis Savidis,Eby G. Friedman
Publisher : Newnes
Release Date : 2017-07-04
Category : Technology & Engineering
Total pages :768
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Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization

Three-Dimensional Integrated Circuit Layout

Three-Dimensional Integrated Circuit Layout
Author : A. C. Harter
Publisher : Cambridge University Press
Release Date : 1991-11-28
Category : Computers
Total pages :207
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First published in 1991, this thesis concentrates upon the design of three-dimensional, rather than the traditional two-dimensional, circuits. The theory behind such circuits is presented in detail, together with experimental results.

Three-Dimensional Integrated Circuit Design

Three-Dimensional Integrated Circuit Design
Author : Yuan Xie,Jingsheng Jason Cong,Sachin Sapatnekar
Publisher : Springer Science & Business Media
Release Date : 2009-12-02
Category : Technology & Engineering
Total pages :284
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We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

Three-Dimensional Integrated Circuit Design

Three-Dimensional Integrated Circuit Design
Author : Yuan Xie,Jingsheng Jason Cong,Sachin Sapatnekar
Publisher : Springer
Release Date : 2009-12-10
Category : Technology & Engineering
Total pages :284
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We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

Three-dimensional Integrated Circuit Design

Three-dimensional Integrated Circuit Design
Author : Vasilis F. Pavlidis,Eby G. Friedman
Publisher : Morgan Kaufmann
Release Date : 2010-07-28
Category : Technology & Engineering
Total pages :336
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With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits. * Demonstrates how to overcome "interconnect bottleneck" with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers * The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find * Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D * Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

Three Dimensional Integrated Circuit Design and Test

Three Dimensional Integrated Circuit Design and Test
Author : Jing Xie
Publisher : Unknown
Release Date : 2015
Category :
Total pages :129
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The emerging three-dimensional integrated circuits (3D ICs) is one of the most promising solutions for future IC designs. 3D stacking enables much higher memory bandwidth and much lower overhead in multi-power domain design, which provides solutions for chip-multiprocessor design in mitigating the "memory wall" and "dark-silicon" problem. At the same time, 3D technology leads to new opportunities and challenges in the field of circuit and system design techniques, EDA tools and chip testing mechanism. This dissertation presents two killer applications for the modern 3D system and one 3D testing solution. The first contribution of this dissertation is to propose a killer application for TSV based system - the 3D memory stacking. This dissertation presents a 3D memory stacking system that leverages the massive number of TSVs between memory layers to help high-bandwidth checkpointing/restore. To validate the proposed scheme, 2-layer TSV-based SRAM-SRAM 3D-stacked chip is implemented to mimic the high-bandwidth and fast data transfer from one memory layer to another memory layer, so that the in-memory checkpointing/restore scheme can be enabled for the future exascale computing. The capacity of each SRAM layer is 1 Mbit. Each layer contains 64 banks, with each bank contains 256 words and the word length is 64-bit. The final footprint including I/O pad is 2.9mm X 2mm. The SRAM dies were taped out in GlobalFoundries using its 130nm low power process, and the 3D stacking was done by using Tezzaron's TSV technology. The prototyping chip can perform checkpointing/restore at the speed of 4K/cycle with 1Ghz clock.This dissertation also gives an applicable solution for 3D testing. Testing for 3D ICs based on through-silicon-via (TSV) is one of the major challenges for improving the system yield and reducing the overall cost. The lack of pads on most tiers and the mechanical vulnerability of tiers after wafer thinning make it difficult to perform 3D Known-Good-Die (KGD) test with the existing 2D IC probing methods. This dissertation presents a novel and time-efficient 3D testing flow. In this Known-Good-Stack (KGS) flow, a yield-aware TSV defect searching and replacing strategy is introduced. The Build-in-Self-Test (BIST) design with TSV redundancy scheme help improve the system yield for today's imperfect TSV fabrication process. Our study shows that less than 6 redundant TSVs is enough to increase the TSV yield to 98% for a TSV cluster with a size under 16 X 16 with relatively low initial TSV yield. The average TSV cluster testing and self-fixing time is about 3-16 testing cycle depending on the initial TSV yield.The second killer application for 3D system in this dissertation is multi-power domain system design utilizing the monolithic technology. Optimizing energy consumption for electronic systems has been an important design consideration. Among all the techniques, multi-power domain design is a widely used one for low power and high performance applications. In order to perform the data transfer between these different power domains, we needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all require dual power rails, which results in large area and performance overhead. We proposed a scan-able CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. It also has built-in scan feature which makes it testable. Our design separates power rails in each tier, substantially reduced physical design complexity and area penalty. The design is implemented in a 20nm, 28nm and 45nm low power technology. It shows 20%-35% smaller D to Q comparing with normal designs. The proposed design also shows scalability and better energy consumption than precious LCFF design.Finally, we presented a dual power domain deep pipeline circuit architecture for future power-efficient systems. We reduce the power consumption by putting all the combinational logics in a lower power domain, while all the FFs and clock network operate at normal voltage for smaller insertion delay and better clock control. In order to realize these functions and system benefits, we proposed a novel level conversion flip flop omega design, which has 30% insertion delay than the normal flop design and could be easily integrated into today's synthesis flow. This work provides guideline on how to design a dual power domain system with less power under the same system throughput requirement. A system level estimation shows that the 3D dual power supply system could consume about 15% less energy by using our design methodology.

Designing TSVs for 3D Integrated Circuits

Designing TSVs for 3D Integrated Circuits
Author : Nauman Khan,Soha Hassoun
Publisher : Springer Science & Business Media
Release Date : 2012-09-23
Category : Technology & Engineering
Total pages :76
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This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits. It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks. Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.

Three-Dimensional Integrated Circuits

Three-Dimensional Integrated Circuits
Author : Guangyu Sun,Yibo Chen,Xiangyu Dong,Yuan Xie,Jin Ouyang
Publisher : Foundations and Trends(r) in E
Release Date : 2011-05
Category : Computers
Total pages :166
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Presents the background on 3D integration technology, and shows the major benefits offered by 3D integration. EDA design tools and methodologies for 3D ICs are reviewed. The cost of 3D integration is also analyzed.

Repair Methodology and Repairable Design of Three-Dimensional Integrated Circuit

Repair Methodology and Repairable Design of Three-Dimensional Integrated Circuit
Author : 周永發
Publisher : Unknown
Release Date : 2011
Category :
Total pages :129
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Reliable Design of Three-Dimensional Integrated Circuits

Reliable Design of Three-Dimensional Integrated Circuits
Author : Shengcheng Wang
Publisher : Unknown
Release Date : 2018
Category : Design
Total pages :129
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Physical Design for 3D Integrated Circuits

Physical Design for 3D Integrated Circuits
Author : Aida Todri-Sanial,Chuan Seng Tan
Publisher : CRC Press
Release Date : 2017-12-19
Category : Technology & Engineering
Total pages :397
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Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.

W-band Three-dimensional Integrated Circuits Utilizing Silicon Micromachining

W-band Three-dimensional Integrated Circuits Utilizing Silicon Micromachining
Author : Katherine Juliet Herrick
Publisher : Unknown
Release Date : 2000
Category :
Total pages :129
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Three-Dimensional Integrated Circuits Design for Thousand-Core Processors: From Aspect of Thermal Management

Three-Dimensional Integrated Circuits Design for Thousand-Core Processors: From Aspect of Thermal Management
Author : Chiao-Ling Lung
Publisher : Unknown
Release Date : 2012
Category : Technology
Total pages :129
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Three-Dimensional Integrated Circuits Design for Thousand-Core Processors: From Aspect of Thermal Management.

Design Automation and Analysis of Three-dimensional Integrated Circuits

Design Automation and Analysis of Three-dimensional Integrated Circuits
Author : Shamik Das
Publisher : Unknown
Release Date : 2004
Category :
Total pages :176
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(Cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.

Electronic Design Automation Challenges in Three-dimensional Integrated Circuits (3D ICs)

Electronic Design Automation Challenges in Three-dimensional Integrated Circuits (3D ICs)
Author : Paul Falkenstern,Schreyer Honors College
Publisher : Unknown
Release Date : 2008
Category :
Total pages :142
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